"Interrupts" to control program flow in a computer have been in use for some time, particularly when the operation of the computer must be synchronized with external events. The word "interrupt" is intended for purposes of the present invention to mean a signal which is internally or externally generated and recognizable by a central processing unit of a general purpose computer as a command to discontinue its current program of instructions and to begin a new subprogram of instruction. The computer may or may not be redirected back to the interrupted program upon completion of the subprogram. Most computers have some type of interrupt handling capability which may differ considerably from one type to another.
The present invention was developed primarily to provide interrupt handling capability for a microcpomputer system having a very limited memory, such as, for example, the MCS-8 system manufactured for commercial sale by the Intel Corporation. The MCS-8 has a single chip central processing unit, hereinafter referred to simply as a CPU, which is an 8-bit parallel processor that is capable of addressing only 16,384 eight bit words of memory. This processor has a limited amount of interrupt handling capability of its own. It will recognize an interrupt signal and can transfer program control from one point to another through a "call" or "jump" instruction. In a call instruction the sequence of addresses in the computer memory, which the central processing unit is currently using to locate its instructions, may be changed to a new sequence. Because it is a call instruction as opposed to a jump instruction, the address of the next instruction in the present sequence is saved within the CPU and control may be later returned to the present sequence by use of a return instruction. For interrupt servicing, the CPU will recognize a signal byte call instruction. This call instruction is hereinafter called a restart instruction and must be generated by external circuitry as part of an interrupt cycle. The CPU contains several internal data storage registers as well as an accumulator register which are used for temporary data storage and data manipulation. In addition, two of these internal registers are used for addressing an external memory for reading and writing data. The CPU also stores internally four status bits identified as the carry, zero, parity, and sign bit respectively, which are set according to the result of each arithmetic operation, and which may be tested for conditional branching. In the normal sequence of a program, these registers and status bits contain pertinent data and information for the proper execution of that program. If, however, the CPU receives and recognizes an interrupt and begins executing a new program with the intention of returning to the interrupted program, the data and information contained in these internal registers at the time the interrupt occurred, must be saved or stored in some manner so that the condition that existed when the interrupt occurred may be restored when control is restored to the original program. It should be noted here that the CPU automatically stores the sequential program address upon execution of the restart instruction for later recall with a return instruction. There is no internal provision, however, for storing the register data or status bits. It is also impossible to store this information in the usual external memory because two of the registers containing data to be saved are used for addressing the external memory. The present invention permits the data to be saved and restored by the use of the computer system output and input instructions along with a special dedicated memory system.